BU2365FV-E2【PDF 11/11 页】IC CLOCK GEN W/VCXO SSOP-B24

DS650F1

CS4461

4.3

Power-Up Sequence

Reliable power-up can be accomplished by keeping the device in reset until the power supplies and clocks

are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the min-

imum specified operating voltages to prevent power glitch related issues.

The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a de-

lay between the release of reset and the generation of valid output, due to the finite output impedance of

FILT+ and the presence of the external capacitance.

4.4

Overflow Detection

The CS4461 includes modulator overflow detection, indicated on pin 15, OVERFLOW (open drain, active

low). OVERFLOW will go to a logical low as soon as an overrange condition is detected. The data will re-

main low until the condition is cleared.

4.5

Grounding and Power Supply Decoupling

As with any high resolution converter, the CS4461 requires careful attention to power supply and grounding

arrangements if its potential performance is to be realized. Figure 1 shows the recommended power ar-

rangements, with VA and VDP connected to clean supplies. VDP, which powers the digital logic, may be

run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no

additional devices should be powered from VDP. Decoupling capacitors should be as near to the ADC as

possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be

kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulator. The FILT+

and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path

from FILT+ to GND. The CDB44800 evaluation board demonstrates the optimum layout and power supply

arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.

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